The present patent application relates to controlling direct memory access (DMA) transfers between a host and an input/output (I/O) device. More particularly, the control is accomplished with reduced overhead.
Direct memory access (DMA) is typically used to transfer large amounts of data between a host central processing unit (CPU) and a DMA input/output (I/O) device. Briefly, the host CPU provides the DMA I/O device with information about where to place (for input) or from where to fetch (for output) data from host memory such that the I/O device independently from the data transfer operation. As a result of the I/O device independently performing the I/O operation, the host CPU is relieved of handling much of the processing associated with the I/O operation.
The information about where to place or from where to fetch, among other information describing and/or controlling the to-be-performed data transfer, is known as xe2x80x9coverhead information,xe2x80x9d and the overhead information is typically transferred from the host CPU to the I/O device in association with the data transfer. For example, the volume of data to be transferred may be so large that it does not fit contiguously into the host memory. In this case, different regions of the host memory may be utilized and the locations of these different regions are conveyed to the I/O device in the transfer of overhead information from the host CPU.
A fundamental metric DMA performance metric is the ratio of the amount of overhead data transferred to the amount of actual data transferred. For example, it is believed that the 21143 PCI/CardBus 10/100 Ethernet LAN Controller, from Intel Corporation of Santa Clara, Calif., requires a transfer of between 32 and 64 bytes of overhead data per DMA transfer. Thus, if a DMA transfer is about 60 bytes, then this mounts to 50% efficiency (or perhaps more properly, inefficiency) in the data transfer.
A plurality of direct memory access data transfers are accomplished to transfer data from a host to an adaptor. For each transfer, an indication of locations of at least one group of storage locations associated with the host available to hold the data to be transferred to the host is provided from the host to the adaptor. An indication of the provided indication is maintained, for that transfer, by the host. Based on the indication of locations provided from the host to the adaptor, data is transferred to the at least one group of storage locations from the adaptor. An indication is provided from the adaptor to the host that the data transferring step has been completed with respect to the at least one group of storage locations. The host determines the locations corresponding to the at least one group of storage locations based on the indications maintained by the host and retrieving the data from the at least one group of storage locations based on the determination.
A similar method is provided to transfer data from the adaptor to the host.
Broadly speaking, the host and adaptor retain state information between DMA data transfers. As a result, absolute values of overhead items need not be transferred between the host CPU and the I/O device for each DMA data transfer, and the amount of overhead is reduced.